手册:416页
PLL4 (also referred to as an Audio PLL) - This is a fractional multiplier PLL used
for generating a low jitter and high precision audio clock with standardized audio
frequencies. The PLLs oscillator frequency range is from 650 MHz to 1300 MHz,
and the frequency resolution is better than 1 Hz....
手册:772页
18.8.9 Numerator of Audio PLL Fractional Loop Divider Register
(CCM_ANALOG_PLL_AUDIO_NUM)
This register contains the numerator (A) of Audio PLL fractional loop divider.(Signed number),
absolute value should be less than denominator
Field Description
31–30- Always set to zero (0).
A 30 bit numerator of fractional loop divider.
手册:773页
18.8.10 Denominator of Audio PLL Fractional Loop Divider
Register (CCM_ANALOG_PLL_AUDIO_DENOM)
This register contains the Denominator (B) of Audio PLL fractional loop divider.(unsigned number)
Field Description
31–30- Always set to zero (0).
B 30 bit Denominator of fractional loop divider.
1. 比起音频PLL和视频PLL,系统PLL(System_PLL or 528_PLL)更合适我的应用,三者的寄存器中都有30位的分数分频设置(),但奇怪的是系统PLL在所有描述的地方都没有提到该功能(只提到了PFD0~PFD3),好像不支持一样?
Numerator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_NUM) <<--除了这里,手册中其它地方从没有提到
Denominator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_DENOM)
2. 另外系统PLL的展频功能(528MHz System PLL Spread Spectrum RegisterCCM_ANALOG_PLL_SYS_SS)有什么用呢?