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uint8_t Dmx512_RX[4][520];
void usartRX_dmaTX_Enable(void)
{
crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK,TRUE);
crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);
dmamux_enable(DMA2, TRUE);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_irq_enable(USART1_IRQn, 0, 1);
usart_init(USART1, 250000, USART_DATA_8BITS, USART_STOP_2_BIT);
usart_clock_config(USART1, USART_CLOCK_POLARITY_HIGH, USART_CLOCK_PHASE_1EDGE,USART_CLOCK_LAST_BIT_NONE);
usart_parity_selection_config(USART1, USART_PARITY_NONE);
usart_hardware_flow_control_set(USART1, USART_HARDWARE_FLOW_NONE);
usart_transmitter_enable(USART1, TRUE);
usart_receiver_enable(USART1, TRUE);
usart_dma_transmitter_enable(USART1, TRUE);
usart_dma_receiver_enable(USART1, TRUE);
usart_rs485_mode_enable(USART1, TRUE);
usart_interrupt_enable(USART1, USART_ERR_INT, TRUE);
usart_interrupt_enable(USART1, USART_IDLE_INT, TRUE);
usart_enable(USART1, TRUE);
dma_reset(DMA2_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = 520;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)Dmx512_RX[0];
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART1->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_USART1_RX);
dma_channel_enable(DMA2_CHANNEL1, TRUE);
}
void USART1_IRQHandler()
{
dma_channel_enable(DMA2_CHANNEL1, FALSE);
dma_init_struct.buffer_size = 520;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)Dmx512_RX[0];
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART1->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
dma_channel_enable(DMA2_CHANNEL1, TRUE);
usart_flag_clear(USART1,USART_FERR_FLAG);
if((Dmx512_RX[0][0] == 0)&&(usart_flag_get(USART1, USART_IDLEF_FLAG) != RESET))
{
usart_flag_clear(USART1,USART_IDLEF_FLAG);
uint8_t DR_text = USART1->sts;
DR_text = USART1->dt;
MyDmaCopy_Channel1(&DmxRX_Buffer[0][5],&Dmx512_RX[0][1]);
Havedata_flagA = 1;
}
}
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