自制脱机烧录SWD协议

杀神归来了

自制一个SWD协议的脱机烧录工具，可以实现读写F1，F0，F4，但是在具体实现批量写FLASH时，发现F1，F0的flash是半字操作的，把CSW寄存器设置成SIZE域设置成 b001 Halfword (16 bits) ，TAR设置0x08000000 ,成功写入，使用TAR地址自增模式 写入失败，发现TAR是32位地址自增，所以每个32位的数据都只写了一半？？？怎么才能连续写入？

后来不使用自增模式，第一次写入0x08000000（16位操作），写入成功，第二次0x08000002，写入失败

杀神归来了

已解决，******************************
采用16位传输时，注意 Packed transfers Mode ARM_debug_interface_v5.pdf  146页

详细解释如何实现16位传输 ：

8.2.7 Packed transfers

If packed transfers are supported they are enabled by setting the auto address increment field, AddrInc, in
the CSW register to b10, Increment packed. See Auto-incrementing the Transfer Address Register (TAR) on
page 8-9.
When packed transfers are enabled, each access to the DRW results in one of the following actions,
depending on the value of the Size field in the field in the CSW, see Variable access size for memory
accesses on page 8-13:
• when Size = b010, word, there is a single word (32-bit) access
• when Size = b001, halfword, there are two halfword (16-bit) accesses
• when Size = b000, byte, there are four byte (8-bit) accesses.
Note
It is IMPLEMENTATION DEFINED whether a MEM-AP supports packed transfers. However, if a MEM-AP
supports access sizes smaller than word it must also support packed transfers.
When packed transfers are enabled, after each successful memory access the address held in the Transfer
Address Register is automatically updated by the access size.
Accesses are always made in increasing memory address order:
• for write accesses to memory, data is unpacked from the DRW in byte-lanes that depend on the
memory address of each write access
• for read accesses, data is packed into the DRW in byte-lanes that depend on the memory address of
each read access.
The byte lanes for data packing and unpacking are the same as those described in Table 8-3 on page 8-14.
This is shown in the following examples:
• Example 8-1 on page 8-17, Halfword packed write operation on a little-endian MEM-AP on
page 8-17
• Example 8-2 on page 8-17, Halfword packed write operation on a big-endian MEM-AP on page 8-17
• Example 8-3 on page 8-18, Byte packed write operation on a little-endian MEM-AP on page 8-18
• Example 8-4 on page 8-18, Halfword packed read operation on a little-endian MEM-AP on
page 8-18.


**************
Example 8-1 Halfword packed write operation on a little-endian MEM-AP


This example describes a single word (32-bit) write access to the DRW on an little-endian MEM-AP with
the following settings:
• Size, CSW[2:0] = b001, to give halfword (16-bit) memory accesses
• AddrInc, CSW[5:4] = b10, to give packed transfer operation
• TAR[31:0] = 0x00000000, to define the base address of the access.
Two write transfers are made. The little-endian halfword entries in Table 8-3 on page 8-14 define the
byte-laning for these accesses. The accesses are made in the following order:
1. TAR[1]=0, so write DRW[15:0] to address 0x00000000.
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000002.
2. TAR[1]=1, so write DRW[31:16] to address 0x00000002.
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000004.

****************

Example 8-2 Halfword packed write operation on a big-endian MEM-AP

This example shows a similar transfer to Example 8-1, but on a big-endian MEM-AP. The operation is a
single word (32-bit) write access to the DRW, with the following settings:
• Size, CSW[2:0] = b001, to give halfword (16-bit) memory accesses
• AddrInc, CSW[5:4] = b10, to give packed transfer operation
• TAR[31:0] = 0x00000000, to define the base address of the access.
Two write transfers are made. The big-endian halfword entries in Table 8-3 on page 8-14 define the
byte-laning for these accesses. The accesses are made in the following order:
1. TAR[1]=0, so write DRW[31:16] to address 0x00000000.
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000002.
2. TAR[1]=1, so write DRW[15:0] to address 0x00000002.
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000004.

*****************************************

Example 8-3 Byte packed write operation on a little-endian MEM-AP

This example describes a single word (32-bit) write access to the DRW on an little-endian MEM-AP with
the following settings:
• Size, CSW[2:0] = b000, to give byte (8-bit) memory accesses
• AddrInc, CSW[5:4] = b10, to give packed transfer operation
• TAR[31:0] = 0x00000002, to define the base address of the access.
Four write transfers are made. The little-endian byte entries in Table 8-3 on page 8-14 define the byte-laning
for these accesses. The accesses are made in the following order:
1. TAR[1:0]=b10, so write DRW[23:16] to address 0x00000002.
After this transfer, the value in the TAR is increased by the transfer size, 1, and becomes
0x00000003.
2. TAR[1:0]=b11, so write DRW[31:24] to address 0x00000003.
After this transfer, the value in the TAR is increased by the transfer size, 1, and becomes
0x00000004.
3. TAR[1:0]=b00, so write DRW[7:0] to address 0x00000004.
After this transfer, the value in the TAR is increased by the transfer size, 1, and becomes
0x00000005.
4. TAR[1:0]=b01, so write DRW[15:8] to address 0x00000005.
After this transfer, the value in the TAR is increased by the transfer size, 1, and becomes
0x00000006.

*****************************************************************************************************

Example 8-4 Halfword packed read operation on a little-endian MEM-AP


This example describes a single word (32-bit) read access to the DRW on an little-endian MEM-AP with
the following settings:
• Size, CSW[2:0]= b001, to give halfword (16-bit) memory accesses
• AddrInc, CSW[5:4] = b10, to give packed transfer operation
• TAR[31:0] = 0x00000002, to define the base address of the access.
Two read transfers are made. The little-endian halfword entries in Table 8-3 on page 8-14 define the
byte-laning for these accesses. The accesses are made in the following order:
1. TAR[1]=1, so read a halfword from address 0x00000002, and pack this value into DRW[31:16].
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000004.

2. TAR[1]=0, so read a halfword from address 0x00000004, and pack this value into DRW[15:0].
After this transfer, the value in the TAR is increased by the transfer size, 2, and becomes
0x00000006.

a20084666

发出你的资料，大家一起帮你想办法

momojiang

改了CSW寄存器的size位和addrinc位，只能写入第一次数据是什么情况